Role Summary
In this role, you will drive early-stage validation of complex SoC and subsystem designs using FPGA/HAPS platforms. You will collaborate with various teams to deliver high-fidelity prototypes that enable software development and system integration.
Experience Level
Entry to Mid-Career, with preference for candidates who enjoy hands-on bring-up, debug, and system-level problem solving.
Responsibilities
- HAPS/FPGA Prototyping & SoC Mapping: Partition large SoC RTL for multi-FPGA platforms, perform synthesis and optimization for FPGA builds, develop build infrastructure.
- Platform Bring-Up & Validation: Bring up prototypes in lab environments, validate system functionality, enable pre-silicon software development.
- Debug & Issue Resolution: Drive debug of issues across FPGA and RTL, analyze data, work across teams to resolve issues.
- Cross-Functional Collaboration: Partner with design teams to ensure RTL is prototype-ready, collaborate with software teams.
Requirements
- Education Requirements: Bachelor's degree in electrical/computer engineering or related field. Masters preferred.
- Technical Skills: Strong RTL design background using SystemVerilog/Verilog; experience with Synopsys HAPS or equivalent; familiarity with SoC buses and protocols; strong debug skills.
- Software / Scripting: Expertise in scripting/automation: Python, Perl, Tcl, Make/CMake.
- Soft Skills: Strong problem-solving skills; excellent communication; self-starter with ability to drive issues to closure.