FPGA Design & Formal Verification Engineer

Role Summary

The Advance Formal Verification team at AMD focuses on providing functional and security verification for a range of intellectual properties (IPs), including various high-speed connections and protocols. We are seeking qualified candidates to fill roles that center on formal verification methodologies and IP verification.

Experience Level

We are looking for professionals at a senior level who have significant experience in formal verification and can lead verification activities. Candidates should have a strong background in FPGA and ASIC verification.

Responsibilities

Responsibilities include collaborating with architects and designers, creating formal verification plans, writing and debugging verification properties, enhancing runtime efficiency with formal methods, and reporting on project status. Senior-level duties involve leading a small team of engineers, mentoring junior staff, developing verification procedures, and resolving complex verification challenges.

Requirements

Ideal candidates should possess a strong background in FPGA designs using Verilog, SystemVerilog, or VHDL. Experience in FPGA debugging, formal property verification, and high-speed protocols is preferred. Knowledge of formal verification tools such as VC-Formal and Questa Formal is beneficial. Strong analytical and communication skills are essential.

Education Requirements

A Bachelor’s degree or higher in Electronics, Electrical, or Computer Engineering is required.