FPGA Design & Formal Verification Engineer

Role Summary

The Advance Formal Verification team is focused on providing formal verification for a variety of intellectual properties (IPs), including PCIe Root-Complex/End-Point and high-speed inter-chiplet connections. Candidates will apply advanced verification methodologies to ensure high design quality for new IPs.

Experience Level

This position is suitable for candidates at both early and senior careers, particularly those with expertise in formal verification methodologies and team leadership capabilities.

Responsibilities

The key responsibilities include:

• Collaborating with architects and designers to understand design intents.
• Creating and executing formal verification plans for design blocks.
• Writing and debugging verification properties and analyzing signatures for resolution.
• Optimizing runtime and improving formal setups.
• Collecting and reporting verification status and progress.
• For senior roles: leading a small verification team, training junior engineers, and developing working procedures.

Requirements

The ideal candidate should have strong experience in the following areas:

• Design and implementation of FPGA-based digital systems.
• Proficiency in Verilog/SystemVerilog/VHDL.
• Experience with in-system FPGA debugging.
• Strong background in formal property verification, sequential equivalence checking, and formal methods.
• Familiarity with high-speed protocols (e.g., PCIe, CXL).
• Knowledge of clock domain crossing techniques is a plus.
• Experience with hardware-firmware interaction verification is desirable.

Education Requirements

A Bachelor’s degree or higher in Electronics, Electrical, or Computer Engineering is required.