Digital Design Engineer Intern

Role Summary

This internship position for summer 2026 is designed for university students pursuing a bachelor's or master's degree, with a requirement of not graduating before September 2026 and not after May 2027. The intern will be engaged in the design and development of high-speed DDR memory interface IC products at our Duluth, Georgia location, contributing to various projects under the supervision of experienced engineers.

Experience Level

This internship is suitable for students who are currently enrolled and have foundational understanding in digital design engineering. Candidates must possess a strong willingness to learn and adapt to new challenges.

Responsibilities

• Develop a small functional block, including documentation, RTL, and simulation.
• Run lint, CDC/RDC checking, and logical equivalence checking tools.
• Create RTL generation scripts.
• Automate data processing to integrate between tools.
• Contribute to synthesis and perform static timing analysis.
• Analyze performance data.

Requirements

• Full-time enrollment in a university degree program in engineering or a relevant field.
• Knowledge of Verilog/SystemVerilog.
• Problem-solving skills and the ability to learn quickly.
• A positive attitude towards undertaking new challenges.
• Knowledge or experience in digital design flows, UVM verification methodology, or software development is advantageous.
• Experience with Python, Tcl, bash, and version control systems like git is a plus.

Education Requirements

Must be currently enrolled in a university program pursuing a bachelor's or master's degree with graduation dates that fall between September 2026 and May 2027.