Digital Design Engineer

Role Summary

AMD is seeking motivated individuals for the Digital Design Engineer position specializing in the microarchitectural design and RTL implementation of PCI Express (PCIe) and Compute Express Link (CXL) IP for next-generation products.

Experience Level

Level - Mid-Career

Responsibilities

• Microarchitectural design and RTL implementation of IP features.
• Participate in design specification and RTL code reviews.
• Collaborate with the Design Verification team to execute on design features.
• Analyze RTL design for power and timing optimization.
• Establish and configure infrastructure for ELAB/CDC/Lint/UPFG flows.
• Deploy and manage integration environments for RTL design.
• Coordinate with integration teams to implement and optimize workflows.
• Configure and maintain P4 (Perforce) repositories and file structures.

Requirements

• 2+ years of overall design experience in the ASIC industry.
• Familiarity with industry standard high-speed protocols such as PCIe, CXL, SATA/SAS, USB.
• Knowledge in digital design and RTL implementation.
• Understanding of synthesis and timing analysis for achieving timing closure.
• Experience in HDL (VHDL/Verilog), HVL (SystemVerilog) and SystemVerilog Assertions (SVA).
• Experience in design with multiple clock domains.
• Proficiency in Makefile and scripting languages like Perl, Python, and Ruby.
• Experience with Electronic Design Automation (EDA) Tools.

Education Requirements

BS (or higher) degree in Electronics/Electrical or Computer Engineering desired.