Digital Design Engineer

Company Overview

AMD specializes in innovative computer hardware, focusing on products that drive next-generation computing experiences.

Role Summary

The Digital Design Engineer will engage in microarchitectural design and RTL implementation for AMD’s PCIe and CXL IP. This role requires collaboration with IP architects to facilitate the execution of advance design projects for servers, clients, and GPUs.

Experience Level

Mid-Career professionals with at least 2 years of experience in ASIC design, particularly in environments requiring technical expertise in digital communications and RTL programming.

Responsibilities

The key responsibilities for this role include:

• Microarchitectural design and RTL implementation of IP features.
• Conduct design specification and RTL code reviews.
• Collaborate with Design Verification for successful feature execution.
• Analyze RTL for power and timing optimization.
• Establish infrastructure for ELAB/CDC/Lint/UPFG flows.
• Manage integration environments for RTL design.
• Cooperate with integration teams to optimize workflows.
• Maintain P4 repository and file structures.

Requirements

Candidates should possess the following qualifications:

• 2+ years design experience in the ASIC sector.
• Familiarity with high-speed protocols like PCIe and CXL.
• Solid background in digital design and RTL implementation.
• Understanding synthesis and timing analysis for timing closure.
• Proficiency in HDL (VHDL/Verilog) and HVL (SystemVerilog).
• Experience with multiple clock domain designs.
• Awareness of Makefile and scripting languages (Perl, Python, Ruby).
• Experience using Electronic Design Automation (EDA) Tools.

Education Requirements

A Bachelor’s or higher degree in Electronics, Electrical, or Computer Engineering is preferred.