DFX Design Engineer

Role Summary

We are seeking a motivated DFx engineer to join our S3 SOC DFX team. In this role, you will contribute to the next generation of AMD’s silicon innovation while developing your expertise in DFx methodologies and advanced design practices.

Experience Level

Level - Mid-Career

Responsibilities

• The successful candidate will own/lead the DFX Design architecture and implement cutting edge DFX features including SCAN, ATPG, MBIST, BSCAN, etc.
• Work closely with the DFX Architecture and the various IP Design teams to align on the DFX requirements and successfully implement the DFX design.
• Design and develop correct by construction DFX design and support DFX verification.
• Work closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects.
• Work with the Synthesis and PD team to ensure correct DFT implementation and timing closure.
• Provide post silicon support to ensure successful bring up.

Requirements

• Experience and understanding of ASIC DFX, synthesis, simulation and verification flow and experience of working in DFX architecture of complex SOC.
• Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration.
• Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem.
• Experience in End-to-End DFX flow development/creation.
• Expert in at least one of the scripting tool (Perl, Python, TCL) and ability to create complex flows/scripts that provide scalable solutions to DFX implementation.
• Strong EDA tools experience (Tessent, Design Compiler, Spyglass).
• Proficient in doing basic unit-level verification using simulations.
• Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.
• Exposure to Static timing analysis & Timing closure is required.
• Scan/ATPG patterns & test flows development, debug, test, and characterization.
• Excellent hands-on debug skills and scripting skills are critical.
• Strong communication skills and the ability to collaborate effectively within a global team environment are essential.
• Strong problem-solving skills.
• Knowledge & experience of low power concepts, clock gating, power gating is a plus.
• Experience with post-silicon bring up is a plus.

Education Requirements

Bachelors or Masters degree in computer engineering or Electrical Engineering.