DFX Design Engineer

Role Summary

We are looking for a skilled DFX Design Engineer to join our S3 SOC DFX team. The successful candidate will be instrumental in driving the next generation of silicon innovation, honing expertise in DFx methodologies and advanced design practices.

Experience Level

Candidates are expected to have experience and understanding of ASIC DFX, synthesis, simulation and verification flow, ideally having worked on DFX architecture of complex SOCs.

Responsibilities

The incumbent will:

• Lead the DFX Design architecture, implementing advanced DFX features such as SCAN, ATPG, MBIST, and BSCAN.
• Collaborate with DFX Architecture and various IP Design teams to align on requirements and successfully implement designs.
• Develop accurate DFX designs and support DFX verification processes.
• Coordinate with RTL designers and Verification Engineers to expedite the identification of functional defects.
• Work with synthesis and PD teams for correct DFT implementation and timing closure.
• Provide support for post-silicon bring up.

Requirements

Applicants should possess:

• Experience in RTL development using Verilog/System Verilog.
• A strong grasp of automated design flows for DFT features in complex SOC ASIC designs or IP subsystems.
• Expertise in at least one scripting tool (Perl, Python, TCL) for creating scalable solutions.
• Familiarity with EDA tools such as Tessent, Design Compiler, and Spyglass.
• Ability to perform basic unit-level verification using simulations and exposure to static timing analysis and timing closure.
• Knowledge of scan/ATPG patterns, development and debugging of test flows.
• Good communication, collaboration skills within global teams, and strong problem-solving capabilities.
• Understanding of low power concepts, clock gating, and power gating is a plus.
• Experience with post-silicon bring up is also favorable.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.