DFT-Timing Engineer

Role Summary

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.

Experience Level

Level - Mid-Career

Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, hardware, firmware, and software driver use cases.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build directed and random verification tests.
• Debug test failures to determine root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.

Requirements

• Proficient in IP level ASIC verification and debugging firmware and RTL code using simulation tools.
• Proficient in using UVM testbenches and working in Linux and Windows environments.
• Experienced with Verilog, System Verilog, C, and C++.
• Knowledge of graphics pipeline.
• Experience developing UVM based verification frameworks and testbenches.
• Automating workflows in a distributed compute environment.
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process.
• Good understanding and hands-on experience in UVM concepts and SystemVerilog language.
• Working knowledge of SystemC and TLM.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset.
• Exposure to video codec system or other multimedia solutions is desirable.

Education Requirements

• Bachelors or Masters degree in Computer Engineering or Electrical Engineering.