DFT Timing Engineer

Role Summary

The DFT Timing Engineer is responsible for planning, constructing, and executing the verification of new and existing features within AMD's graphics processor IP. The role emphasizes producing a final design that is free of bugs.

Experience Level

This is a mid-career level position requiring experience in processor architecture, digital design, and verification, along with excellent collaboration skills across different engineering teams.

Responsibilities

Key responsibilities include:

• Collaborating with architects and hardware/firmware engineers to comprehend new features for verification.
• Creating test plan documentation that considers interactions among various components.
• Estimating the time necessary for writing feature tests and alterations to the test environment.
• Developing both directed and random verification tests.
• Debugging test failures to identify root causes and collaborating with engineers to address design issues.
• Reviewing functional and code coverage metrics to adjust tests accordingly.

Requirements

The role requires experience and skills that include:

• Proficiency in IP level ASIC verification and debugging firmware/RTL code using simulation tools.
• Experience with UVM testbenches in both Linux and Windows environments.
• Knowledge of Verilog, System Verilog, C, C++, and graphics pipelines.
• Experience in developing UVM-based verification frameworks and automating workflows in distributed computing environments.
• Familiarity with simulation profiling tools and automated efficiency improvement processes.
• Hands-on experience with SystemC and TLM, along with scripting languages such as Perl, Ruby, or shell.

Education Requirements

A Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering is required.