DFT Lead

Role Overview

The DFT Lead position within the AECG SSD ASIC group at AMD involves implementing advanced Design-for-Test (DFT) methodologies for ASIC products. This role focuses on enhancing the testing and debug capabilities of AMD's cutting-edge silicon designs. Successful candidates will collaborate with various teams across AMD to ensure the integrity and functionality of complex designs.

Experience Level

This position is suitable for applicants at a mid-career level with extensive experience in DFT processes and ASIC design environments.

Key Responsibilities

• Implementation and verification of DFT and DFD architecture and features.
• Managing scan insertion and ATPG (Automatic Test Pattern Generation) pattern generation.
• Conducting ATPG verification through gate-level simulations.
• Anaylzing test coverage and reducing test costs.
• Providing post-silicon support, ensuring successful bring-up and yield learning.
• Collaborating with cross-functional teams on DFT and DFD methodologies.
• Performing RTL design and integration related to DFT.
• Documenting DFT processes and maintaining specifications.
• Creating CAD tools and scripts supporting DFT logic integration in SoC designs.
• Debugging and support during the initial silicon bring-up.

Candidate Profile

Successful candidates should demonstrate strong attention to detail and problem-solving abilities while effectively communicating across teams. They should also possess experience with various DFT methodologies and a solid grounding in ASIC design.

Education Requirements

A Bachelor's or Master’s degree in computer engineering or electrical engineering is required for this role.