DFT Design Engineer

Role Summary

The DFT Design Engineer role involves managing the entire DFT lifecycle, ensuring test solutions are implemented effectively from specification definition to post-silicon bring-up. The engineer will work closely with various teams to deliver successful project outcomes.

Experience Level

This position is suited for candidates with a strong background in Design-for-Test methodologies and a proven ability to work in a collaborative environment.

Responsibilities

The key responsibilities include:

• Implementing and verifying DFT and Design-for-Debug (DFD) architectures.
• Inserting Scan, JTAG, and Boundary Scan chains; generating ATPG patterns.
• Generating, implementing, and verifying Memory Built-In Self-Test (BIST) logic.
• Applying low power DFT techniques to designs.
• Aching DFT timing closure and verifying ATPG patterns through gate-level simulation.
• Analyzing test coverage and reducing test costs.
• Providing post-silicon support to ensure successful bring-up and improving yield learning.

Requirements

Candidates should possess:

• Strong understanding of Design For Test methodologies and DFT verification standards.
• Experience with Tessent TestKompress and Silicon Scan Network.
• Proficiency in VCS simulation tools, Perl/Shell scripting, and Verilog RTL design.
• Exposure to static timing analysis processes.
• Experience in pre-silicon test planning and engagement with design teams.
• Strong analytical skills to enhance test coverage and yield.
• Effective communication skills for teamwork across global teams.
• Knowledge of low power design concepts is a plus.

Education Requirements

A Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field is required.