DFT Design Engineer

Job Title

DFT Design Engineer

Role Summary

Design and deliver Design-for-X (DFT/DFD/DFV) features for SoC and IP to enable testability, debug and validation for high-volume manufacturing. Work across architecture, RTL implementation, pre- and post-silicon validation and cross-functional teams (logic, validation, circuit, physical design, HVM).

Part of a central engineering team focused on product enablement and manufacturability; responsible for DFx architecture, RTL integration, ATPG/ATVG flows and supporting silicon debug and yield improvement.

Experience Level

Senior — expects extensive industry experience (typically 8–10+ years in SOC/IP DFx design and verification).

Responsibilities

Primary responsibilities span DFx micro-architecture, RTL implementation and validation activities.

• Define DFx architecture and strategy (TAP, BSCAN, Scan, MBIST, IO DFX, debug ports) to meet testability, debug and manufacturability goals.
• Oversee scan/ATPG definition, design, verification and documentation; generate and validate ATPG patterns.
• Implement and integrate DFx RTL, ensure timing convergence, signal/clock connections and zero RTL design errors for DFx features.
• Insert and validate memory BIST and other test logic to support HVM screening and ATE requirements.
• Set direction for pre-silicon validation and collaborate with post-silicon PDE teams to enable manufacturing test capability and silicon debug.
• Perform yield analysis and assist with root-cause analysis and debug across geo-diverse teams.
• Track progress, communicate issues and provide timely indicators and guidance to management.

Requirements

Core technical skills and practical experience required for successful performance in the role.

• Proven experience in SOC/IP DFx design and verification (DFT, DFD, DFV) including creation of DFx plans, schedules and cost estimates.
• Strong RTL design and integration skills for DFx IP; experience with timing closure in collaboration with physical design teams.
• Hands-on experience with ATPG tools and flows (e.g., Mentor Tessent or equivalent) and familiarity with GLS testbenches and pattern validation.
• Experience with MBIST, Scan, BIST, BSCAN, TAP, STF and related DFx building blocks and coverage analysis.
• Proficient in SystemVerilog and RTL verification methodologies (UVM/OVM); strong scripting skills (shell, Perl) and automation experience.
• Strong silicon debug skills, understanding of ATE and high-volume test requirements; able to support post-silicon debug and yield improvement.
• Ability to work independently and lead technical efforts or small teams; effective cross-functional communication skills.

Nice-to-have:

• Familiarity with Unix, Verilog or C programming and RTL integration/validation methodologies.
• Experience using Synopsys VCS and Mentor GLS testbenches or equivalent simulation/debug environments.

Education Requirements

BS in Electrical Engineering, Computer Engineering or related field with a minimum of 10+ years of directly related industry experience; or MS degree with a minimum of 8+ years of directly related industry experience in SOC/IP DFx design and verification. Fields specified: Electrical Engineering, Computer Engineering or related technical disciplines.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.