Role Summary
As a Design Verification Intern at Marvell Technology, you will focus on verifying complex System on Chips (SoCs) through simulation of register-transfer level (RTL) and gate level designs. The role involves close collaboration with design teams and verification engineers to develop and implement verification test plans and drive improvement in verification methodologies.
Experience Level
Entry Level: Currently pursuing a Bachelor’s or Master's Degree in Computer Science, Electrical Engineering, or related fields.
Responsibilities
- Verify complex SoCs through simulation of RTL and gate level designs.
- Collaborate with design and verification engineers to develop and implement verification test plans.
- Develop constrained-random verification test environments using Verilog/System Verilog, UVM, and C programming.
- Create testbenches, checkers, monitors, drivers, and other testbench components.
- Debug failing simulations and create test vectors to thoroughly test designs.
- Analyze test coverage metrics and manage verification deliverables.
Requirements
- Knowledge of advanced digital design, CPU design, and computer architecture.
- Experience with industry standard simulators such as Cadence Incisive, Synopsys VCS, or Questasim.
- Familiarity with HDLs like VHDL, Verilog, or SystemVerilog.
- Experience in standard verification methodology flows, including test plans and testbench development.
- Programming skills in C or C++ and experience with scripting in Python, PERL, or Bash.
- Good problem-solving and critical thinking skills, with strong written and verbal communication abilities.
- Self-starter, goal-oriented, and a team player.
Education Requirements
Bachelor's or Master's Degree in Computer Science, Electrical Engineering, or a related field.