Role Summary
As a Design Verification Engineer, you will work with leading industry tools and methodologies to contribute to the verification of Cache & Memory Management IPs which are a part of the Graphics Core IP (GFXIP). You will collaborate with architects, design engineers, and the verification team to deliver high-quality verification on schedule. Additionally, you will work with Power Attainment teams to meet performance and power targets and may support post-silicon bring-up, diagnostics, and validation teams.
Experience Level
Level - Mid-Career
Responsibilities
- Collaborate closely with architects, RTL designers, and other verification engineers to achieve verification closure within project schedules.
- Create, reuse, and debug testbenches, verification components, and tests for design verification.
- Be responsible for functional, power, and performance verification of blocks, including verification planning, execution, and DV closure.
- Develop and execute test and coverage plans to ensure completeness in functional, performance, and power aspects.
- Adopt evolving verification methodologies to functionally verify increasingly complex SoC designs within aggressive schedules, leveraging existing verification infrastructure.
Requirements
- Strong verification experience in large ASIC development projects.
- Solid understanding of Computer Architecture and Digital Design concepts.
- Proficient in Verilog, System Verilog, and C/C++/OOO coding techniques.
- Experience with UVM, OVM, or equivalent verification methodologies.
- Familiarity with constrained random verification, functional coverage, and assertions.
- Experience with formal verification is a plus.
- Knowledge of scripting languages such as Perl, TCL, Ruby, Bash, or Python.
- Experience with industry-standard tools such as Synopsys VCS, VC Formal, DVE, Verdi, GDB, or equivalent.
- Strong analytical skills and attention to detail.
Education Requirements
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.