Design Verification Engineer - ASIC/UVM/SystemVerilog

Role Summary

We are seeking a high-impact MTS Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high-performance ASIC designs. The ideal candidate brings hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.

Experience Level

Level - Mid-Career

Responsibilities

Key responsibilities include:

• Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
• Drive test plan creation, feature mapping, and coverage strategy for complex networking and data-path IP.
• Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
• Collaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high-quality deliverables.
• Mentor junior engineers and provide technical leadership within the verification team.

Requirements

Required qualifications include:

• Expert-level knowledge of SystemVerilog and UVM.
• Strong hands-on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE).
• Strong debug skills across architecture, RTL, and testbench layers.
• Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation.

Education Requirements

Bachelor’s Degree in Electrical/Computer Engineering or related field. Master's degree preferred.