Design Verification Engineer - ASIC/UVM/SystemVerilog

Role Summary

The Design Verification Engineer at AMD will focus on ensuring the reliability and performance of ASIC designs. This role requires extensive verification expertise and involves hands-on collaboration with various teams responsible for the production of next-generation networking technologies.

Experience Level

This position is targeted towards candidates with substantial experience in design verification, particularly in ASIC, UVM, and SystemVerilog, suitable for mid-career professionals.

Responsibilities

The key responsibilities include the following:

• Develop robust UVM-based testbench architectures for various verification levels.
• Drive test planning and coverage strategies for complex networking IP.
• Execute verification plans, handle regression triage, and debug a range of functional and performance issues.
• Enhance verification methodologies and automation efforts using scripting languages.
• Collaborate cross-functionally with design and validation teams to guarantee deliverable quality.

Requirements

To qualify for this role, candidates must possess:

• Expert-level proficiency in SystemVerilog and UVM.
• Extensive experience with SystemVerilog simulators and waveform debuggers.
• Hands-on background in verifying complex IP or subsystems using thorough test plans.
• Strong debugging skills across architectural and RTL levels.
• Experience with protocols like PCIe, AXI, or similar data-path components.

Education Requirements

A Bachelor’s Degree in Electrical or Computer Engineering is required; a Master's degree is preferred.