Design & Verification Engineer

Job Title

Design & Verification Engineer

Role Summary

The successful candidate will participate in pre-silicon RTL Design and Verification activities related to PCIe Controller Soft IP development and PHY integrations within Rambus's PHY integration team located in France.

Experience Level

Mid-Career

Responsibilities

• Verilog RTL design to integrate different IPs together, such as PCIe IP with vendor PHY module.
• Verifying the IP integration with a dedicated simulation environment.
• Developing and supporting test cases for various verification environments.
• Supporting worldwide customers on IP integration.
• Familiarizing with existing verification processes and proposing improvements.
• Maintaining traceability from customer specifications or product specifications to verification results.
• Tracking and maintaining verification productivity metrics.
• Reporting periodically on progress and difficulties.

Requirements

• "Can Do" attitude.
• Bachelor's or Master's degree in Electronics Engineering, Computer Science, or related disciplines.
• Strong analytical and problem-solving skills.
• Excellent interpersonal skills; ability to work with international teams.
• Willingness to travel abroad.
• Very good English communication skills.
• 6+ years of experience in verification using Verilog, SystemVerilog, and FPGA prototyping.
• 6+ years of experience with complex ASIC/VLSI verification.
• 6+ years of experience with Avery or UVM; experience with third-party VIP is a plus.
• 6+ years of experience in a multinational company.
• Experience with creating documentation, proficiency in Python, shell scripting, etc.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Computer Science, or related disciplines.