Design Verification Engineer

Role Summary

The Design Verification Engineer will be responsible for driving the verification efforts of DDR interfaces, including advanced memory protocols such as DFI, DDR5, and LPDDR5, across a range of DIMMs (Dual In-line Memory Modules).

Experience Level

This position is targeted towards mid-career professionals with significant experience in validation and verification of complex systems.

Responsibilities

• Lead and mentor a team of verification engineers in the development and execution of verification strategies for DDR5, LPDDR5, and DFI memory systems.
• Understand the SOC as a complete system, ensuring FW, BIOS & SW are aligned to enable features of the memory interface.
• Collaborate with IP/Domain architects to assess technical issues and develop solutions.
• Act as a product owner, responsible for architecture analysis and technical solutions for marketing requests.
• Coordinate with design teams for floorplan refinement, verification test plan reviews, and resolution of pre-silicon bugs.
• Support post-silicon teams for product performance and functional issue resolution.

Requirements

• Expert-level knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl.
• Proven track record of multiple tape-out experiences and verification sign-offs.
• Strong communication and presentation skills, with experience in technical publications and executive briefings.
• Experience in developing SystemVerilog based testbenches and functional coverage models.
• Experience with hardware and firmware alignment in memory architectures.
• Experience in building VIPs and BFMs for memory interfaces is preferred.
• Proficiency in system verilog assertions and formal verification methods is required.
• Working knowledge of DFT flows is preferred.

Education Requirements

Bachelor’s or Master’s degree in a related discipline is preferred.