Design Verification Engineer

Title

Design Verification Engineer

Role Summary

The CIT team is seeking an experienced ASIC Design Verification Engineer to participate in all aspects of design verification activities. This role involves using the latest methodologies with automation while focusing on power and performance.

Experience Level

Mid-Career

Responsibilities

• Developing testbenches and verification components such as UVCs, models, BFMs, and reusable verification environments.
• Writing, modifying, and maintaining constraint-random and directed test cases and libraries in System Verilog/UVM.
• Analyzing functional, code, and test plan coverage.
• Implementing assertions, checkers, and monitors.
• Triaging and debugging regressions.
• Deploying industry-leading verification methodologies such as UVM and Formal Verification.
• Reproducing functional bugs found in silicon, in simulation and/or Formal Verification tools.
• Conducting and participating in code reviews.

Requirements

• Strong analytical thinking and problem-solving skills with excellent attention to detail.
• Effective communication and writing skills.
• Good teamwork and interpersonal skills.

Education Requirements

Bachelor's degree in Electrical Engineering or Computer Engineering.