Design Verification Engineer

Role Summary

The Design Verification Engineer for Cellular Baseband will focus on verifying innovative cellular baseband modems and transceiver link controllers. This critical position involves ensuring the quality and reliability of next-generation cellular systems while crafting reusable verification environments using UVM.

Experience Level

This role requires multiple years of relevant industry experience, including leadership experience, in design verification, preferably in a high-performance environment.

Responsibilities

• Develop comprehensive coverage-driven and directed test cases for validating complex IP and subsystem designs.
• Forge methodologies for verification by deploying sophisticated tools and techniques.
• Collaborate with multi-functional teams to drive innovation and ensure tape-out readiness.
• Work closely with product development teams to enhance cellular systems and customer experiences.
• Gain expertise in cellular protocols and advanced debug methodologies.

Requirements

Applicants must have a strong knowledge of System Verilog and UVM, be skilled in System C, C/C++, and/or Python/Perl, and proven experience in developing verification methodologies. Excellent test planning, problem-solving abilities, and advanced communication skills are also essential.

Education Requirements

The preferred candidate will hold a PhD or Master of Science degree in Electrical Engineering or Computer Science, or a Bachelor’s degree with substantial industry experience. Knowledge of cellular physical layer operation and experience with verification of embedded processor cores is advantageous.