Design Verification Engineer

Role Summary

The CIT team at AMD is seeking experienced ASIC Design Verification Engineers to contribute to the advancement of next-generation technologies. This role involves working in all aspects of design verification, ensuring quality RTL and firmware design while focusing on power and performance.

Experience Level

Mid-Career

Responsibilities

• Develop testbenches and verification components such as UVCs, models, BFMs, and reusable verification environments.
• Write, modify, and maintain constraint-random and directed test cases and libraries in System Verilog/UVM.
• Analyze functional, code, and test plan coverage.
• Implement assertions, checkers, and monitors.
• Debug regressions and triage issues effectively.
• Apply verification methodologies such as UVM and Formal Verification.
• Reproduce bugs found in silicon using simulation and/or Formal Verification tools.
• Participate in code reviews and drive continuous improvement.

Requirements

• Significant experience in hardware verification, with expertise in Verilog, System Verilog, and UVM.
• Familiarity with Linux and Windows environments.
• Understanding ASIC design and debugging Verilog RTL code using simulation tools.
• Strong programming skills and experience with Makefile and scripting languages such as Perl, Python, or Ruby.

Education Requirements

Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related technical field.

Office Location

Vancouver, BC (other locations include Markham, ON or Ottawa, ON).