Design Engineer – AI SoC Development

Role Summary

As a Design Engineer in the AI SoC organization, you will focus on developing logic design, register transfer level (RTL) coding, and simulation for SoC designs that power various AI applications.

Experience Level

Experienced Hire

Responsibilities

• Evaluate architectural trade-offs based on features and performance constraints.
• Implement RTL in Verilog/System Verilog and integrate IP blocks at the top level.
• Work closely with verification teams to achieve robust validation and develop timing constraints.
• Support silicon bring-up and post-silicon validation activities.
• Collaborate with senior engineers to improve design methodologies and ensure quality compliance.

Requirements

Minimum qualifications include a Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, along with 4+ years of experience in:

• RTL design and implementation for ASIC/SoC development.
• Proficiency in Verilog/System Verilog for RTL coding.
• Experience with synthesis tools and timing closure methodologies.

Preferred qualifications include understanding clock domain crossings, familiarity with bus protocols, experience with static timing analysis, and proficiency in scripting (Python, TCL, etc.).

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.