CPU Verification Engineer - Unit DV

Role Overview

The CPU Verification Engineer will be part of the AMD Cores design & verification group in Bangalore, India. This role focuses on the development and verification of cutting-edge CPU architectures that are integral to various AMD SoCs. The position involves collaboration with teams across the US and India to enhance the maintainability and scalability of RTL and testbench environments.

Position Summary

In this role, you will be responsible for ensuring the verification of high-level features, developing comprehensive test plans, and implementing both directed and random test cases. You will also need to debug issues and enhance stimulus coverage to guarantee the stability and health of features within the verification process.

Experience Level

This position is suited for candidates with a minimum of 5 years of CPU verification experience. We are looking for individuals who have a strong understanding of computer architecture and digital systems along with experience in verification methodologies.

Key Responsibilities

• Collaborate with stakeholders to understand high-level features and assess cross-feature dependencies.
• Create a detailed high-level test plan that outlines stimulus, debugging, and coverage strategies for feature verification.
• Develop directed and random test cases targeting feature bringup and debug failures, addressing RTL/Verif bugs and testbench issues as they arise.
• Ensure stability in feature health and work on evaluating and optimizing stimulus coverage as required.
• Develop C++ checkers when necessary, while also acquiring deep knowledge of micro-architecture.
• Work towards achieving 100% Feature Coverage (FCOV), collaborating with other feature owners for cross-feature coverage improvements.
• Engage in Post-Si bug recreation as needed.

Essential Requirements

• B.E/B.Tech/M.E/M.Tech in Computer Science, Electrical, or Electronic Engineering.
• 5+ years of experience in CPU verification.
• Strong foundation in computer architecture and digital systems.
• Familiarity with assembly (x86) code.
• Proficient in Verilog, System Verilog, and C++. Knowledge of shell/perl scripting is advantageous.
• Understanding of Formal Verification methodologies, including tools like VSI-FV, JASPER, IFV, or IEV is a plus.
• A proactive and adaptable team player, with effective communication skills, and a capacity to multitask efficiently.

Education Requirements

Candidates must have a B.E/B.Tech/M.E/M.Tech in Computer Science/Electrical/Electronic Engineering.