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Collateral Device Engineer

Intel Corporation
Full-time
Remote friendly (Santa Clara, California, United States)
Worldwide
$190,650 - $269,150 USD yearly
Level - Mid-Career

Role Overview

The MDCE organization focuses on the integration of advanced technology development into practical manufacturing, serving as a critical link between innovation and production for foundry customers.

Position Summary

As a Collateral Device Engineer, you will engage in the development of device collateral as well as the design rule implementation for foundry technology. Your main tasks will include creating test chip designs and optimizing product layouts for high-volume manufacturing.

Experience Level

The ideal candidate will have significant experience, requiring at least a master’s degree in Electrical Engineering, Physics, or related discipline, along with a minimum of 7 years of experience specifically related to CMOS device engineering.

Key Responsibilities

  • Develop device collateral including test chip architectures and layouts to support technology characterization.
  • Collaborate with technology teams to refine design rules and customize collateral for specific customer needs.
  • Manage design-rule waiver processes and documentation for applications.
  • Implement manufacturing collateral to ensure compliance with specifications and yield targets.
  • Analyze device performance data to drive improvements in manufacturability and process control.
  • Provide technical guidance on design rule compliance and risk assessments.
  • Stay updated with industry trends to improve device collateral design methodologies.

Qualifications

Minimum Requirements include a Master's degree in Electrical Engineering or related field with 7+ years in CMOS devices focusing on test chip design. Experience in scribe line layouts, design rule management, and DTCO skills is essential.

Preferred Skills

Preferred qualifications include a Ph.D. with over 5 years in the same field and hands-on experience with advanced test chip designs. Knowledge in DOE principles, DRC development, and SPC is highly regarded.