Cache DFT Verification Engineer

Role Summary

This position focuses on the verification of AMD’s next-generation CPU microprocessors, specifically in maintaining and enhancing existing verification test benches for cache functionality, including DFT features such as MBIST.

Experience Level

This role is suitable for candidates with a solid background in verification techniques for microprocessors or ASIC designs, with a preferred educational background in Electrical Engineering or Computer Engineering.

Responsibilities

The key responsibilities include:

• Performing functional and design for test feature verification of high-speed microprocessor designs.
• Developing infrastructures and test plans for both full chip and stand-alone block-level verification.
• Participating in the development of formal verification techniques.
• Creating an automated regression infrastructure for functional verification.
• Collaborating with engineering teams to define and verify DFT microarchitecture for AMD CPUs.
• Working on product test teams during the test bring-up phase.
• Debugging x86 assembly based directed tests and random exercisers for design validation.
• Resolving simulation discrepancies and assertion responses across both behavioral and gate level logic models.
• Measuring coverage terms, addressing weaknesses, and ensuring project quality objectives are met.
• Developing infrastructure for post-silicon validation and characterization.
• Coordinating with cross-functional teams to meet project deliverables.

Requirements

Required expertise includes:

• Demonstrated experience with Verilog HDL and high-level programming in C/C++, x86 assembly, and Perl.
• Understanding modern computer architecture and DFT features like JTAG -1149.x and MBIST.
• Familiarity with CMOS transistor design and deep sub-micron logic.
• Knowledge of formal verification tools and techniques is a plus.

Education Requirements

A Bachelor’s, Master’s, or PhD in Electrical Engineering or Computer Engineering is preferred.