ASIC Verification Engineer, Senior Staff
SynopsysJob Title
ASIC Verification Engineer, Senior Staff
Role Summary
Senior verification engineer on the Digital and Verification Development team developing and validating complex digital mixed-signal IP for high-speed interfaces targeting Data Center, AI/ML, and 5G applications. The role focuses on building verification environments, executing advanced verification methodologies, and supporting IP bring-up in customer environments.
Experience Level
Senior — 7+ years of experience in design verification.
Responsibilities
The engineer will plan and execute verification activities, build environments from specifications, and drive closure of verification goals.
- Plan tests, checklists, coverage goals, and assertion strategy.
- Create detailed verification environments from functional specifications.
- Apply advanced verification techniques: constrained random, functional coverage, assertions, and formal verification.
- Write and run test cases, checkers, and coverage-driven tests implementing the verification plan.
- Debug simulations, including SystemVerilog-modeled analog signals and mixed-signal scenarios.
- Perform RTL, gate-level (GLS), and co-simulations and ensure coverage closure.
- Participate in technical reviews and provide technical leadership within the team.
- Provide customer support for IP bring-up in customer simulation environments.
- Follow and improve development and verification processes.
Requirements
Must-have technical skills and experience for immediate contribution; additional skills listed as nice-to-have.
Must-have:
- Minimum 7 years of hands-on design verification experience.
- Strong experience with VCS/Verdi simulation tools and formal verification tools (vc_formal).
- Experience debugging simulations and performing RTL, GLS, and mixed-signal co-simulations.
- Proven ability to create verification environments and implement coverage-driven verification.
- Fluent English communication skills and ability to work effectively in a team.
Nice-to-have:
- Experience with UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertions).
- Scripting experience in Perl, TCL, or Python.
- Prior customer support or IP bring-up experience in customer simulation environments.
Education Requirements
BS, MS, or PhD in Electronics Engineering, Electromechanics, or Telecommunications (listed as required in the posting).
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
