ASIC/SOC DFT Engineer

Role Summary

The role involves contributing to the development of next-generation ASICs for deployment in space and ground infrastructures. The engineer will collaborate with cross-disciplinary teams to ensure high-quality design and test setups, enhancing the performance of the Starlink network.

Experience Level

This position requires a minimum of 1 year of professional experience working with ASICs, along with a strong understanding of design tools and methodologies.

Responsibilities

• Evaluate design readiness for scan insertion using RTL and physical design DRC tools.
• Integrate and verify DFT fabrics and IP within subsystems.
• Run and refine scan insertion processes for optimal coverage.
• Conduct ATPG analysis to verify scan chain construction and coverage goals.
• Manage non-timing and SDF annotated gate level simulations.
• Create and validate ATPG content for post-silicon testing through simulations.
• Collaborate effectively with circuit design, ATPG, and manufacturing teams.

Requirements

Candidates must hold a Bachelor’s degree in electrical engineering, computer engineering, or computer science. They should possess at least one year of relevant experience in ASIC development, particularly in scan insertion or DFT setup.

Education Requirements

Bachelor’s degree in electrical engineering, computer engineering, or computer science.