ASIC Digital Verification Engineering Internship

Role Summary

We are seeking an intern to join our ASIC Digital Verification Engineering team in Gdansk, Poland. This internship provides hands-on experience in digital and analog verification environments, utilizing advanced methodologies and tools. The position is designed for individuals eager to dive into real-world projects, collaborating closely with experienced teams.

Experience Level

This is an internship position suitable for students currently pursuing their degrees in relevant fields such as Electronics, Computer Engineering, or Automation. Ideal candidates are expected to have a foundational knowledge of digital electronics along with basic knowledge of analog systems.

Responsibilities

Key responsibilities include:

• Defining and developing complex digital and analog verification environments using SystemVerilog, UVM, and formal verification methodologies.
• Creating verification test plans and documentation for testbench components.
• Running RTL and mixed signal simulations, analyzing results, and collaborating with design teams to optimize designs.
• Developing behavioral models and identifying design issues in digital and analog domains.
• Improving automation and verification toolchains.

Requirements

The candidate should possess:

• Good understanding of digital electronics and basic analog knowledge.
• Working knowledge of Verilog, VHDL, and SystemVerilog.
• Proficiency in at least one programming language such as Python, Perl, C, C++, or MATLAB.
• Understanding of UVM or similar verification methodologies is advantageous.
• Strong communication skills and the ability to work effectively in a team environment.

Education Requirements

The intern should be currently pursuing a degree in Electronics, Computer Engineering, Automation, or a related field.