ASIC Digital Design, Sr Staff Engineer - Serdes IP RTL Design

Role Summary

The ASIC Digital Design, Sr Staff Engineer will be responsible for RTL design and verification of Serdes IP, leading design and implementation efforts.

Experience Level

Mid-Career

Responsibilities

The individual will:

• Lead RTL design for Serdes blocks.
• Collaborate with verification team to ensure functionality.
• Participate in design reviews and code reviews.
• Contribute to performance improvements and optimizations.

Requirements

Candidate must have:

• Extensive experience in ASIC digital design.
• Proficiency in Verilog and system design.
• Ability to work in a team and mentor junior engineers.
• Strong problem-solving skills and attention to detail.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or related field.