ASIC Digital Design Sr. Staff Engineer

Role Summary

The ASIC Digital Design Sr. Staff Engineer will be responsible for developing verification environments and regression test cases for SerDes standards and related digital, analog, and firmware architectures.

Experience Level

6-10 years of hands-on experience in FPGA design and verification, with a focus on IP-level functional verification.

Responsibilities

• Interpreting SerDes standards and developing verification environments in MATLAB.
• Evaluating and troubleshooting digital and mixed-signal circuits for optimal performance.
• Collaborating with teams to solve verification challenges and improve methodologies.
• Adapting internal verification environments to replicate challenging scenarios.
• Identifying and implementing process improvements for efficiency.
• Documenting verification environments and procedures.

Requirements

• Proficiency in Verilog and MATLAB for digital design and FPGA prototyping.
• Strong programming skills in Python, C/C++, and TCL for automation.
• Knowledge of digital and mixed-signal circuit evaluation and troubleshooting techniques.
• Ability to interpret and apply digital architecture and SerDes standards.
• Excellent technical documentation skills.

Education Requirements

Bachelor's degree in Electrical Engineering or related field is typically required.