ASIC Design Verification Engineer

Role Summary

The AMD IOHUB Team is looking for an ASIC Design Verification Engineer to join our team. This role involves developing I/O connectivity and virtualization technologies for data center and machine learning workloads. You will be responsible for various aspects of IP verification including creating verification architecture and defining test plans.

Experience Level

This position is suitable for candidates with a strong background in ASIC verification and digital design.

Responsibilities

• Collaborate with IP architects to develop verification architecture and plans.
• Take ownership of key features in complex IP verification projects.
• Work on test plans, environment development, regression, and closure.
• Develop and maintain verification environments and test cases using System Verilog/UVM/SystemC.
• Debug regressions and analyze coverage.
• Implement industry-leading verification methodologies like UVM.
• Reproduce functional bugs found in Post-Silicon environments.
• Participate in code reviews and develop engineering tools to improve processes.

Requirements

Strong analytical, problem-solving skills, and attention to detail are essential. Effective communication and teamwork abilities are also important. A self-starter mindset is required, as well as the ability to work in a fast-paced environment.

Education Requirements

A BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science is required.