ASIC Design Verification Engineer

Job Title

ASIC Design Verification Engineer

Role Summary

The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Verification Engineer to join our growing team. You will be involved in all aspects of IP verification including creating a verification architecture, defining test plans, developing verification environments, and achieving verification closure and sign-off.

Experience Level

Level - Mid-Career

Responsibilities

• Collaborate with IP architects on verification architecture and development plans.
• Participate in verification of complex IP blocks and take ownership of key features.
• Work on test plans, verification environment development, regression, and coverage closure.
• Develop, modify, and maintain VIP, libraries, verification environments, and test cases using System Verilog/UVM/SystemC.
• Triaging and debugging regressions.
• Analyzing code and functional coverage.
• Deploying verification methodologies such as UVM and formal verification.
• Reproducing functional bugs found in Post-Silicon in simulation environments.
• Conducting and participating in code reviews.
• Develop and maintain scripts and tools for improving engineering infrastructure, methodology, and execution.

Requirements

• Education Requirements: BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science.

• Strong ASIC verification experience.
• Understanding of digital design and computer architecture.
• Proficient in Verilog, System Verilog, C/C++, UVM, OOP, with knowledge of Linux and Windows environments.
• Experience in ASIC design debugging using simulation tools.
• Experience in security verification is an asset.