ASIC Architect

Job Title

ASIC Architect

Role Summary

Senior hardware architect responsible for defining and owning SoC hardware architecture across the full product lifecycle. The role collaborates with design, verification, physical design, systems and software teams to specify architecture features, validate performance/power/area trade-offs, and support post-silicon production and customer delivery.

This is a hands-on leadership role focused on delivering commercially viable ASIC architectures for data infrastructure applications (enterprise, cloud, AI, carrier).

Experience Level

Senior. Role targets experienced architects with extensive industry experience; typically 15+ years of relevant experience in ASIC/SoC architecture or related domains.

Responsibilities

Primary responsibilities include technical leadership, architecture definition, and cross-functional delivery.

• Own hardware architecture for SoC products through concept, design, validation and production support.
• Define detailed architecture specifications and validation plans.
• Collaborate with marketing and business teams to identify product use cases and requirements.
• Coordinate with design, verification, physical design, system and software teams to deliver architecture features.
• Perform performance analyses and evaluate power-performance-area trade-offs for architectural options.
• Apply domain expertise in Embedded CPU subsystems, PCIe interconnects, and data network switching.
• Participate in industry workgroups (PCI-SIG, CXL, OCP) and file patents for novel architecture work.
• Provide post-silicon support including silicon debug and customer documentation.

Requirements

Essential technical skills and professional experience required for the role.

• Proven track record delivering ASIC product architectures and accompanying documentation.
• Experience guiding and mentoring design and verification teams through ASIC implementation.
• Strong written and verbal communication skills.
• Deep understanding of industry-standard interconnect protocols (e.g., PCIe) and system-level interconnects.
• Domain expertise in ARM CPU subsystem architecture and embedded CPU subsystems.
• Knowledge of ASIC security concepts, including root-of-trust and data encryption.

Nice-to-have:

• Experience with data network switching architectures and high-performance SoC networking features.
• Previous participation in standards or industry workgroups.

Education Requirements

Master's degree (MS) in Electrical Engineering or Computer Engineering with 15+ years of relevant experience, or PhD in Electrical Engineering or Computer Engineering with 10+ years of relevant experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.