Application Engineering Staff Engineer - Physical Verification Runset Development

Role Overview

The Application Engineering Staff Engineer for Physical Verification Runset Development plays a pivotal role in advancing semiconductor technology. This position involves working directly with state-of-the-art tools like IC Validator, ensuring the creation of high-performance runsets essential for the semiconductor industry.

Position Summary

The engineer will be tasked with developing and validating DRC, LVS, and Fill runsets while collaborating closely with semiconductor foundries. This role requires hands-on expertise in physical verification, script automation, and the ability to troubleshoot complex verification issues.

Experience Level

The position requires 5-8 years of experience specifically within the Physical Verification domain, including substantial experience with industry-standard EDA tools and strong scripting capabilities.

Core Responsibilities

• Develop and validate runsets for DRC, LVS, and Fill using IC Validator.
• Collaborate with foundries to understand and meet process requirements.
• Automate the qualification processes for IC Validator runsets.
• Troubleshoot verification issues such as LVS discrepancies and DRC violations.
• Directly interface with customers for requirement gathering and support.
• Mentor junior engineers and contribute to team knowledge sharing.
• Stay current with advancements in EDA tools and semiconductor processes.

Necessary Qualifications

Applicants must possess a B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field, coupled with advanced proficiency in EDA tools like IC Validator, Calibre, and scripting in Perl, Tcl, and Python. A comprehensive understanding of CMOS layouts and ASIC design is also essential.

Education Requirements

Candidate must have a minimum of a B.Tech or a higher degree in Electronics, VLSI, or a related field.