Analog Layout Staff Engineer

Role Summary

Marvell Technology, located in Bengaluru, Karnataka, India, is looking for an Analog Layout Staff Engineer to join their Central Engineering Foundational IP team. This role involves developing advanced SerDes IPs using cutting-edge semiconductor technologies.

Experience Level

This position is suitable for candidates with 4 to 8 years of related professional experience in electrical or electronics engineering, microelectronics, or adjacent fields.

Responsibilities

The main responsibilities of the Analog Layout Staff Engineer include:

• Leading development projects for high-speed SerDes IPs.
• Conducting full-custom circuit layout and verification.
• Performing RC extraction and working with various industry physical verification tools.
• Collaborating with global teams to ensure compatibility with advanced semiconductor technologies.
• Engaging in EMIR analysis, ESD design, and layout solutions.

Requirements

Applicants should meet the following criteria:

• Bachelor's, Master's, or PhD degree in Electrical/Electronics Engineering or related fields.
• Experience with mixed-signal, analog, or high-speed layout, including but not limited to SerDes, ADC/DAC, and PLL.
• Familiarity with the Cadence Virtuoso environment and physical verification tools such as DRC, LVS, and DFM.
• Experience with advanced technology nodes (32nm, 28nm, 16nm, 14nm, and FinFET).
• Strong communication skills, self-motivation, and adaptability in a dynamic environment.
• Programming, automation, and circuit design experience are advantageous.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronics Engineering, Microelectronics or other related fields is required.