VLSI Design Verification Manager - Slingshot ASIC Team

Job Title

VLSI Design Verification Manager — Slingshot ASIC Team

Role Summary

Lead verification for HPE Slingshot networking ASICs used in NIC and switch products. Manage a team of approximately 8–15 design verification engineers and own verification methodology, execution quality, and sign‑off readiness across block, subsystem, and full‑chip scopes. This position is designed as onsite with an expectation of primarily working from an HPE office.

Experience Level

Senior — typically 10+ years of VLSI design verification experience; prior people-management experience is expected for this manager role.

Responsibilities

Accountable for verification planning, execution, team development, and program readiness.

• Provide leadership for all phases of pre‑silicon design verification: planning, testbench development, coverage closure, regression management, and sign‑off.
• Define, own, and evolve SystemVerilog/UVM verification methodology and best practices across block, subsystem, and full‑chip scopes.
• Ensure development of robust UVM/SystemVerilog environments: stimulus, scoreboards, checkers, assertions, and functional coverage.
• Drive regression health, failure triage, root‑cause isolation, and closure of design issues in collaboration with logic design and architecture teams.
• Manage project deliverables, schedules, and staffing to meet program milestones and quality goals.
• Recruit, mentor, and develop engineers; set performance expectations and support career growth for junior through senior levels.
• Identify and drive process improvements, reuse, automation, and efficiency in verification workflows.
• Communicate verification status, risks, and sign‑off readiness to management and cross‑functional partners.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Strong hands‑on experience with SystemVerilog and UVM‑based verification methodologies.
• Demonstrated technical leadership in design verification (DV technical lead, block or project verification owner).
• Experience with coverage‑driven verification, regression management, and sign‑off readiness.
• Proficiency with industry EDA simulation tools and large‑scale regression workflows.
• Strong analytical and problem‑solving skills, with excellent written and verbal communication.
• Ability to operate effectively in a multi‑site, cross‑functional engineering environment.
• People leadership skills: mentoring, performance management, and hiring.
• Preferred: direct experience with Synopsys VCS, familiarity with GitHub Enterprise Cloud workflows and AI tools, and familiarity with high‑performance networking (Ethernet, SERDES, PCIe) or HPC/AI systems.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. The posting indicates equivalent practical experience is acceptable in lieu of a degree.

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.