Static Timing Analysis Engineer

Job Title

Static Timing Analysis Engineer

Role Summary

The Physical Design Timing Engineer will perform static timing analysis and optimize timing for system-on-chip (SoC) designs to meet performance and power targets. The role partners with architecture, clocking, logic design and backend teams to deliver validated timing models and integration-ready timing solutions.

Experience Level

Senior-level engineer. Candidates are expected to have substantial hands-on experience in physical design timing analysis and delivery; see Education Requirements for degree-equivalent guidance.

Responsibilities

Core responsibilities focus on timing analysis, constraint development, and cross-team integration for chip- and block-level timing.

• Perform static timing analysis and timing optimization at block and chip level to meet functional and performance goals.
• Generate, verify, and maintain timing constraints; identify and resolve timing violations during development.
• Conduct timing rollups and set PVT conditions for analysis based on product operating modes.
• Develop and implement power-optimized clock networks and support clocking partitioning strategies.
• Define and refine timing-modeling methodologies to improve physical design efficiency and quality.
• Collaborate with architecture, clock design, logic design, and backend teams to achieve clocking balance and optimal power delivery.
• Validate integration flows and partner with clocking teams to refine chip-level timing solutions.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Proficiency with static timing analysis tools and established timing methodologies.
• Demonstrated expertise in timing modeling, verification, constraint generation, and optimization techniques.
• Practical understanding of process, voltage, temperature (PVT) impacts and how to apply them in timing analysis.
• Experience applying timing analysis to SoC-level designs, including clocking and partitioning considerations.
• Strong collaboration and communication skills for working across multiple engineering teams.

Nice-to-have:

• Advanced knowledge of SoC development and clocking design principles.
• Experience in high-performance computing or low-power design environments.
• Record of defining methodologies that improve physical design throughput and quality.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is required by the posting; Master's or PhD in a related field is acceptable with reduced experience thresholds. The role defines experience thresholds tied to degrees (8+ years with a Bachelor's, 6+ years with a Master's, 4+ years with a PhD), and equivalent practical experience is considered in lieu of a degree per those thresholds.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.