Staff SoC Physical Verification Engineer, HBM

Job Title

Staff SoC Physical Verification Engineer, HBM

Role Summary

The Physical Verification Engineer is a technical contributor in the Heterogeneous Integration Group responsible for defining, executing, and owning sign-off physical verification flows for HBM logic die and memory-centric SoCs through tape-out.

The role works across physical design, EDA tool teams, foundries, and product engineering to deliver full-chip verification (DRC, LVS, ERC, DFM, reliability) and to close verification issues under aggressive schedule and quality constraints.

Experience Level

Senior-level — typically 10+ years of relevant industry experience; expectation of mentoring and driving methodology improvements.

Responsibilities

Primary technical responsibilities and cross-functional interactions for chip sign-off and manufacturability.

• Lead end-to-end physical verification sign-off for full-chip and hierarchical designs including DRC, LVS, ERC, PERC, antenna, and DFM.
• Execute and debug foundry-qualified rule decks, manage waivers, and drive clean closure to foundry requirements.
• Perform reliability verification across power domains: ESD, latch-up, electromigration, floating nets, and connectivity checks.
• Run density, metal fill, and CMP checks to ensure yield-aware manufacturability at advanced nodes (3 nm and below).
• Perform parasitic RC extraction and support correlation of verification results with post-silicon measurements.
• Develop, maintain, and optimize verification flows, automation, and regression infrastructure using scripting and automation tools.
• Drive adoption of ML/AI-based verification and PPA optimization tools where applicable.
• Partner with physical design, custom layout, CAD, RTL, product engineering, EDA, and foundry teams from design kick-off through tape-out readiness and sign-off.

Requirements

Must-have technical skills and experience; preferred items are noted.

• Strong experience with full-chip or block-level physical verification for advanced-node SoC, memory, or heterogeneous integration designs.
• Hands-on expertise in physical verification methodologies: DRC, LVS, ERC, PERC, DFM, antenna, and reliability sign-off.
• Experience using industry tools such as Calibre, IC Validator (ICV), Pegasus, or similar, including rule deck development or customization.
• Working knowledge of RTL-to-GDS implementation flows, including place-and-route and extraction, and their impact on verification outcomes.
• Proven ability to drive verification closure with strong cross‑functional communication in a global engineering environment.
• Experience with scripting and automation for verification flows (Python, Tcl, Perl, or similar).
• (Nice-to-have) Experience with HBM, DRAM, multi-die/chiplet or 2.5D/3D integration and high-performance CPU/GPU/accelerator implementations.
• (Nice-to-have) Familiarity with foundry DRC/FEOl/BEOL rules, post-silicon failure analysis, yield learning, and layout-based debug.

Education Requirements

Preferred: Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience. The posting explicitly references 10 or more years of relevant industry experience as the typical expectation for this role.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.