Staff SoC DFT Engineer, HBM

Job Title

Staff SoC DFT Engineer, HBM

Role Summary

Join a SoC design team responsible for high‑bandwidth memory (HBM) base‑die designs. The role owns SoC‑level design for test (DFT) architecture and implementation to ensure manufacturability, testability, and successful silicon bring‑up across HBM generations.

Experience Level

Senior — requires seven or more years of relevant SoC/DFT experience.

Responsibilities

Deliver DFT solutions across block, subsystem, and chip levels and coordinate with integration, verification, physical design, and manufacturing teams.

• Define and drive SoC‑level DFT architecture early in the design cycle, aligning with integration, floorplanning, timing, power, and physical constraints.
• Implement scan insertion, MBIST/LBIST, boundary scan (JTAG), and test access architectures for HBM base‑die designs.
• Integrate DFT logic with RTL and SoC teams; support ATPG readiness and coverage closure.
• Execute and sign off DFT flows: linting, CDC checks, DFT rule checks, ATPG readiness, and coverage analysis.
• Collaborate with physical design to optimize placement, routing, timing closure, and DRC/LVS signoff for test logic.
• Work with verification, product engineering, test, probe, and manufacturing to support pre‑silicon debug and post‑silicon bring‑up.
• Partner with CAD and methodology teams to standardize and improve DFT flows and mentor junior engineers.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Hands‑on experience with SoC DFT architecture and implementation: scan insertion, MBIST/LBIST concepts, boundary scan, and ATPG.
• Experience across full RTL‑to‑GDS flows and collaboration with synthesis, static timing analysis (STA), and physical design teams.
• Proficiency with industry EDA tools (Siemens, Synopsys, and/or Cadence) for DFT and implementation.
• Experience executing sign‑off DFT flows, including CDC checks, DFT rule checks, and coverage closure.
• Strong RTL debugging and design analysis skills; ability to drive technical decisions and partner cross‑functionally.
• Seven or more years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs/SoCs.

Education Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.