Staff Engineer, Physical Design

Job Title

Staff Engineer, Physical Design

Role Summary

Lead and execute full-chip and block-level ASIC physical implementation for foundation IPs and test chips at advanced process nodes. The role focuses on taking synthesized netlists to signoff-quality GDSII, improving flows through automation, and mentoring engineers to ensure robust manufacturable designs.

Experience Level

Senior-level — typically 6+ years of hands-on ASIC physical design implementation and tapeout experience.

Responsibilities

Deliver and improve physical implementation flows and ensure designs meet timing, power, area, and manufacturing requirements.

• Drive physical design from synthesized netlist through floorplanning, placement, CTS, routing, optimization, and GDSII signoff.
• Execute block-level and full-chip place-and-route flows using industry-standard tools and methodologies.
• Lead timing closure across multi-corner multi-mode (MCMM) scenarios; resolve setup, hold, and signal integrity issues.
• Perform parasitic extraction, IR drop analysis, and electromigration checks to ensure power integrity and reliability.
• Manage physical verification signoff (DRC, LVS, ERC) and resolve foundry-specific violations to readiness for tapeout.
• Implement low-power design techniques using UPF/CPF, including multi-voltage domain management and isolation/retention strategies.
• Develop and maintain automation scripts (Tcl, Perl, Python, Shell) to improve flow efficiency and repeatability.
• Establish reusable methodologies, accelerate time-to-signoff, and mentor junior engineers on physical-design best practices.

Requirements

Must-have technical skills and practical experience required to perform the role; nice-to-have items listed where applicable.

• Must-have: Proven track record of taking ASIC designs to tapeout and meeting signoff criteria.
• Must-have: Deep expertise in physical-design flows: floorplanning, power planning, placement, CTS, routing, and optimization.
• Must-have: Experience with industry tools such as Cadence Innovus, Synopsys ICC2, or equivalent.
• Must-have: Strong proficiency in static timing analysis using tools like PrimeTime or Tempus and closing timing in complex MCMM scenarios.
• Must-have: Hands-on experience with physical verification and signoff tools such as Calibre or ICV.
• Must-have: Experience implementing low-power design flows (UPF/CPF) and power-aware closure across multiple voltage domains.
• Must-have: Proficiency in scripting for automation and flow development (Tcl, Perl, Python, Shell).
• Nice-to-have: Experience with advanced nodes (7nm and below) and foundry-specific flow adaptation.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.