Staff Engineer, Physical Design

Job Title

Staff Engineer, Physical Design

Role Summary

Lead block- and subsystem-level physical implementation and closure for complex hierarchical SoCs at advanced process nodes. The role focuses on timing, congestion, power integrity, and clocking at the subsystem level while collaborating closely with SoC-level teams to ensure integration and alignment.

Experience Level

Senior — minimum 8+ years of experience in physical design with subsystem-level closure for complex SoCs.

Responsibilities

Deliver high-quality physical implementation and improve subsystem-level closure methodologies. Work cross-functionally to identify and mitigate risks.

• Lead block- and subsystem-level timing closure, congestion mitigation, and physical implementation quality.
• Collaborate with SoC-level teams on clocking strategies, floorplanning intent, and integration requirements.
• Ensure subsystem clock domains integrate with SoC clock architecture (clock domain partitioning, CT architecture, skew management, clock gating).
• Develop and scale closure flows, methodologies, and automation to improve predictability and execution efficiency.
• Mentor and guide physical design engineers, promoting best practices and methodology adoption.
• Coordinate with RTL, STA, power, verification, and backend teams for smooth handoffs and closure.
• Proactively identify, assess, and mitigate physical design risks and drive solutions with SoC teams.

Requirements

Must-have technical skills and hands-on tool experience for subsystem physical design.

• Minimum 8 years of experience in physical design focused on subsystem-level closure for hierarchical SoCs.
• Expertise in timing closure, constraint management, congestion analysis and resolution, and power-aware implementation.
• Strong understanding of clocking methodologies: domain partitioning, clock tree architecture, skew management, and clock gating.
• Hands-on experience with industry tools such as Synopsys ICC2 / Fusion Compiler / PrimeTime and Cadence Innovus / Tempus / Certus.
• Experience with signoff and analysis platforms.
• Proficiency in scripting and automation (Tcl, Python, and/or Perl).
• Deep knowledge of end-to-end SoC design flows and proven cross-functional collaboration across timing, power, clocking, verification, and backend teams.
• Strong understanding of low-power design techniques and power-aware implementation methodologies.

Education Requirements

BTech or MTech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.