Staff Design Verification Engineer - Coherent Interconnect

Job Title

Staff Design Verification Engineer - Coherent Interconnect

Role Summary

Staff-level individual contributor responsible for verification of a next-generation cache-coherent interconnect subsystem with emphasis on CXL protocol behavior, bridge/adapter paths, and subsystem integration.

Work across architecture, RTL, formal, software, and verification teams to ensure correct coherent data movement, ordering, flow control, QoS, and error handling across multiple interfaces.

Experience Level

Senior (Staff). Requires 7+ years of ASIC/SoC design verification experience; this is a Staff / T4 individual-contributor role.

Responsibilities

Own and drive verification for coherent interconnect subsystem behavior and integration; improve verification quality and reuse across the interconnect effort.

• Plan and execute verification for subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths with emphasis on CXL flows.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for coherency, ordering, backpressure, flow control, buffering, QoS, and error handling.
• Define directed and constrained-random scenarios that expose corner cases in coherency, concurrency, ordering, credits, arbitration, latency-sensitive and bandwidth-sensitive flows.
• Collaborate with architecture, RTL, formal, and software teams to clarify specs, close ambiguities, and improve verification quality.
• Analyze failures, isolate root cause across specification/RTL/testbench, and drive durable fixes.
• Contribute reusable methodology, infrastructure, and automation to scale the horizontal interconnect verification effort.
• Mentor engineers and raise verification practices through reviews and technical guidance.

Requirements

Must-have skills and experience for this role.

• 7+ years of hands-on ASIC/SoC design verification ownership at block- or subsystem-level appropriate for a Staff role.
• Strong protocol knowledge in CXL and at least one of CHI, ACE, AXI, or similar high-performance interconnects.
• Proven experience with SystemVerilog and UVM-based verification and building reusable verification infrastructure.
• Deep understanding of cache-coherent systems, on-chip interconnects, memory-subsystem behavior, ordering, and flow-control semantics.
• Experience creating test plans, assertions, coverage models, scoreboards, and debug workflows for complex hardware subsystems.
• Strong debugging and root-cause analysis skills across specification, RTL, and testbench layers.
• Strong scripting and automation skills (Python or similar).
• Effective communicator able to work across architecture, RTL, and verification teams in a fast-moving environment.

Nice-to-have:

• Direct experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs.
• Experience with protocol-conversion or bridge-heavy subsystems, especially with CXL-oriented validation.
• Familiarity with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug.
• Experience mentoring engineers and influencing verification quality beyond immediate ownership.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.