Staff Design Verification Engineer

Job Title

Staff Design Verification Engineer

Role Summary

Join a mixed‑signal design and verification team focused on high‑speed SerDes IP (MIPI C‑PHY/D‑PHY, PCIe, USB, SATA, Ethernet, DisplayPort) used in automotive, mobile, and data center applications. Lead verification from test plan creation through RTL and gate‑level regressions to coverage closure.

Collaborate with digital, analog and architecture engineers to ensure verification meets product requirements and to improve verification efficiency, including prototyping AI‑assisted techniques.

Experience Level

Senior-level. The role expects approximately 5+ years of ASIC verification experience, particularly in digital or mixed‑signal IP verification.

Responsibilities

Primary responsibilities include developing verification plans, building and extending UVM testbenches, executing regressions, and closing coverage for SerDes IP.

• Create test plans for mixed‑signal SerDes IP including MIPI C‑PHY and D‑PHY.
• Develop and extend UVM testbenches using constraint‑random methodologies; modify agents, scoreboards, and sequences.
• Write SystemVerilog tests validating digital and mixed‑signal interaction across RTL and gate‑level simulations.
• Run RTL and GLS regressions, analyze failures, debug root causes, and coordinate fixes with design teams.
• Drive code and functional coverage closure; identify untested scenarios and write directed or constrained‑random tests.
• Prototype AI‑driven verification techniques for test generation, coverage analysis, or regression triage.
• Collaborate with analog, digital, and architecture teams to align verification with design intent.

Requirements

Must-have skills are listed first; nice‑to‑have items follow.

• Must-have: 5+ years of ASIC verification experience focused on digital or mixed‑signal IP.
• Must-have: Strong hands‑on experience writing complex SystemVerilog testcases for functional verification.
• Must-have: Proven experience developing UVM‑based testbenches (agents, scoreboards, sequences).
• Must-have: Proficiency with Python or similar scripting languages for automation and regression management.
• Must-have: Familiarity with RTL and gate‑level simulation flows, coverage analysis, and regression debug.
• Nice‑to‑have: Experience with high‑speed interfaces such as MIPI, PCIe, USB, SATA, Ethernet, or DisplayPort.
• Nice‑to‑have: Mixed‑signal verification experience or prior work with co‑simulation teams.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.