Staff Chip Design Engineer

Job Title

Staff Chip Design Engineer

Role Summary

Hands-on senior engineer who combines RTL/IP design and verification with machine-learning workflows to provide training data, reference designs, and domain expertise that enable autonomous chip-design tooling. You will develop RTL libraries and IP, build benchmarks and datasets, and work closely with ML and software teams to translate silicon constraints into actionable inputs for model training.

Onsite role in Redwood City, CA; you will operate within a research-heavy, cross-functional team focused on increasing design velocity and correctness of generated designs.

Experience Level

Senior — typically 12+ years of relevant experience in RTL design, verification, or equivalent combined experience.

Responsibilities

Key duties include hands-on RTL/IP development, verification, and collaboration with ML and software teams to create assets for an autonomous design flow.

• Partner with ML and software teams to translate silicon constraints into training signals and design requirements.
• Design and deliver high-quality RTL libraries, processor blocks, and reusable IP.
• Build and maintain benchmarks, reference designs, and datasets used to evaluate tooling and increase design velocity.
• Execute end-to-end design methodologies from architectural spec to synthesized netlists and bitstreams to identify optimization opportunities for AI.
• Generate and curate large datasets of syntactic and semantic hardware code for model training and robustness.
• Implement and maintain verification environments, including SystemVerilog/UVM testbenches and assertions.
• Perform hands-on debugging with simulators, waveform analysis, and coverage collection.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Must-have: 12+ years of experience in RTL design or substantial combined design/verification experience.
• Must-have: Proficiency in SystemVerilog/UVM for verification and Python for design automation.
• Must-have: Experience with AMD/Xilinx (Vivado, Vitis), Altera/Intel (Quartus) toolchains, or ASIC physical-design flows, including SoC and IP integrations.
• Must-have: Practical knowledge of industry communication protocols (Ethernet, PCIe, CXL, DDR5, NoC).
• Must-have: Hands-on debugging experience (simulators, waveform viewers, coverage tools) and building verification infrastructure.
• Must-have: Strong written and verbal communication to explain chip design concepts to software and AI teams.
• Nice-to-have: Familiarity with open-source EDA tools and ecosystems (Verilator, Cocotb, Yosys, OpenSTA).
• Nice-to-have: Experience across multiple chip-flow stages (validation, synthesis, physical design) and writing timing/constraint files (SDC/XDC).
• Nice-to-have: Demonstrated machine-learning or deep-learning project experience relevant to hardware/EDA.
• Other: Comfortable working in a dynamic, research-oriented startup environment.

Education Requirements

Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a closely related field is expected; equivalent practical experience is acceptable. The role also references demonstrated coursework or project experience in machine learning/deep learning.

About the Company

Company: Cognichip

Headquarters: Redwood City, CA, USA

Cognichip is an AI-driven semiconductor startup developing autonomous chip design tools, RTL libraries, IP blocks, and benchmarks that combine machine learning with silicon engineering to automate and accelerate semiconductor design flows.