Staff Analog Layout Engineer

Job Title

Staff Analog Layout Engineer

Role Summary

Staff Analog Layout Engineer responsible for designing and delivering complex analog/mixed-signal physical layouts within the Central Engineering group. Work covers deep sub-micron, FinFET and emerging GAA process technologies with ownership from planning through tape-out.

You will mentor junior layout engineers, collaborate with circuit designers, close physical verification and reliability issues, and contribute to layout methodology and automation. This role may require eligibility for access to export‑controlled technology.

Experience Level

Senior-level; typically requires 6–10 years of experience in high-speed analog/custom layout development.

Responsibilities

Primary responsibilities include:

• Independently develop complex analog/mixed-signal and custom layouts using Cadence Virtuoso, Mentor, and similar tools for deep sub-micron, FinFET and GAA processes.
• Mentor and review the work of junior layout engineers; provide guidance on best practices and optimization.
• Collaborate with circuit designers to translate schematic intent into efficient, high-performance layouts.
• Drive closure of physical verification issues (DRC, LVS, ERC, ANT) and ensure verification readiness for tape-out.
• Perform EMIR simulations, identify IR drop and electromigration issues, and implement layout fixes to meet reliability targets.
• Lead layout reviews and contribute to internal process and methodology improvements.
• Own layout blocks from floorplan through tape-out and support post-delivery verification and fixes.
• Develop and maintain automation scripts (Perl, Tcl, SKILL) to streamline layout tasks and improve productivity.

Requirements

Must-have qualifications:

• 6–10 years of hands-on experience in high-speed analog/custom layout development.
• Proven track record delivering high-speed or precision analog circuits, preferably across multiple process nodes.
• Strong understanding of local layout effects in advanced technology nodes.
• Expertise in matching, signal/clock routing, shielding, RC reduction, biasing, and power routing techniques.
• Experience with EMIR, latch-up, ESD strategy, and power planning.
• Proficiency with CAD/layout tools and physical verification flows.
• Ownership mindset and excellent communication skills for coordinating with global teams.

Nice-to-have: experience across multiple process nodes and prior work on automation for layout flows.

Education Requirements

BE/B.Tech or MS/M.Tech in Electronics & Communication (E&C), Electrical & Electronics Engineering (EEE), or related Electrical Engineering fields (Bachelor's or Master's) from a reputable institution. The posting emphasizes technical degrees in electrical/electronics disciplines.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.