Job Title
Sr. Staff Engineer, Analog IC Design
Role Summary
Senior analog IC design engineer responsible for architecting and designing high-performance analog and mixed-signal circuits for SerDes and related transceiver functions. Works within the CE-AMS analog design team and collaborates with DSP, digital, layout, and validation teams to deliver production-ready IP.
Experience Level
Senior. The posting specifies 2+ years of experience as a baseline.
Responsibilities
Primary duties include hands-on analog design, cross-functional architecture work, and support through characterization and product bring-up.
- Design analog circuit blocks for high-speed SerDes and transceivers (e.g., CTLE, FFE, DFE, CDR, PLL, line drivers).
- Participate in SerDes architecture development with DSP, analog, and digital teams.
- Define and coordinate IP characterization and validation plans with application engineering.
- Perform pre-tapeout system-level analog validation and sample lab bring-up and debugging.
- Provide guidance and instructions to layout engineers; review layout impact on high-speed designs.
- Support product and customer engineering activities, including documentation and technical communication.
Requirements
Key technical skills and experience required or strongly expected.
- Strong fundamentals in analog circuit design for high-speed applications.
- Proven experience designing analog blocks used in SerDes and transceivers (PLL, data converters, oscillators, CTLE, FFE, DFE, CDR, line drivers).
- Proficiency with analog design and verification tools, including Cadence Virtuoso, Spectre, ADE, and post-layout extraction tools.
- Knowledge of signal integrity, noise reduction techniques, and Multi-GHz low-jitter clock generation and distribution.
- Good understanding of analog layout in FinFET technologies and its impact on high-speed designs.
- Experience with system-level pre-tapeout validation and lab chip bring-up and debug.
- Strong communication and documentation skills; able to coordinate across teams and support customers.
- Experience working in advanced process nodes (e.g., 3nm, 2nm) is advantageous.
Education Requirements
Master's degree and/or PhD preferred in Electrical Engineering or related fields; the posting references these degrees specifically. The job also cites a baseline of 2+ years of experience. (No explicit mention of alternative "equivalent experience" language was provided.)
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.

Date Posted: 2026-05-22