Silicon Validation Manager

Job Title

Silicon Validation Manager

Role Summary

Manage a silicon validation team responsible for PHY and functional validation of high-bandwidth switch devices in a post-silicon lab environment. The role focuses on PCIe physical and protocol layers, SERDES characterization, lab bring-up, and cross-functional debugging with design, software, and external vendors.

The team supports advanced process nodes and packaging for datacenter switch products and is accountable for defining and executing overall validation and test plans and delivering verified silicon to customers.

Experience Level

Senior — managerial role. Requires multiple years of hands-on silicon validation and at least three years managing validation teams; typical total industry experience is 5–7+ years depending on background.

Responsibilities

Primary responsibilities include lab-based validation, test plan ownership, and cross-functional issue resolution.

• Own management of PHY and functional silicon validation in a post-silicon environment.
• Define, document, execute, and report overall validation and test plans for switch devices.
• Lead lab bring-up and unit test execution focused on PCIe physical and PCS layer hardware and firmware; extend testing to protocol layers.
• Perform high-speed signal validation and analysis (Eye diagram, jitter, BER) using oscilloscopes, BERTs, and network analyzers.
• Analyze and debug PHY and protocol issues for storage and network interfaces (PCIe, UALink, Ethernet).
• Troubleshoot failing tests using diagnostics, software tools, hardware analyzers, logic/protocol analyzers, and meters.
• Lead technical discussions, coordinate with cross-functional teams and external vendors to resolve post-silicon and customer issues.
• Work closely with silicon design, software engineering, and customers to triage design issues and debug failure cases.

Requirements

Must-have technical skills, experience, and leadership for the role.

• Minimum 3+ years managerial experience in silicon validation.
• Strong understanding of high-speed SERDES, equalization techniques, and PCIe, UALink, and Ethernet protocols.
• 5+ years of hands-on experience with high-speed I/O testing, debugging, and validation.
• Strong lab skills and practical experience with system bring-up, system testing, and hardware/software debug.
• In-depth working knowledge of SERDES characterization equipment (oscilloscope, BERT, network analyzer, etc.).
• Strong analytical, problem-solving, and communication skills.

Nice-to-have / preferred:

• Practical PCIe interface and characterization experience.
• Experience with Ethernet and/or UALink protocols.
• Knowledge of physical and protocol layers (PIPE I/F, PCS, MAC) of high-speed interfaces.
• Ability to read board schematics and understand board layout.
• SERDES modeling techniques and working experience with Python.

Education Requirements

Required: Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 7+ years of relevant experience, OR a Master’s degree or PhD in Computer Science, Electrical Engineering, or related fields with 5+ years of relevant experience. No certifications were specified. (Degrees and years taken from the job posting.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.