Senior Staff RTL Design Engineer

Job Title

Senior Staff RTL Design Engineer

Role Summary

Lead RTL microarchitecture and implementation for high-performance mixed-signal connectivity IP (UCIe, DDR, Die-to-Die) on a Bengaluru-based engineering team. Drive designs from specification through tape-out, coordinate across design, verification, physical design, and validation, and provide hands-on technical leadership and mentorship.

Experience Level

Senior — typically 8+ years of hands-on RTL/IP/ASIC design experience.

Responsibilities

You will own technical delivery and integration of RTL blocks and related activities:

• Own RTL design and implementation for high-performance mixed-signal IP blocks (UCIe, DDR, Die-to-Die).
• Develop microarchitecture from specification and drive design reviews through tape-out.
• Write clean, synthesizable Verilog and SystemVerilog with emphasis on reusability and coding standards.
• Collaborate with analog designers, verification, physical design, and validation to close timing and resolve cross-domain issues.
• Drive synthesis, lint, CDC analysis, DFT insertion, and timing closure using industry-standard EDA tools.
• Debug functional and timing failures, analyze coverage gaps, and support silicon bring-up and post-silicon validation.
• Author microarchitecture specs, integration guides, and design rationale for internal and customer use.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Must-have: 8+ years of hands-on RTL design experience for IP, ASIC, or SoC development.
• Must-have: Strong proficiency in Verilog and SystemVerilog for synthesizable RTL coding and performance-oriented coding practices.
• Must-have: Solid experience with logic synthesis, static timing analysis, CDC, and DFT concepts using industry-standard EDA flows.
• Must-have: Proven ability to debug complex functional and timing issues across large, multi-block designs.
• Must-have: Scripting experience (Python, TCL, or Perl) to automate flows and improve productivity.
• Must-have: Experience driving design reviews, documenting design rationale, and mentoring junior engineers.
• Nice-to-have: Familiarity with protocols such as AMBA, PCIe, UCIe, or DDR; prior tape-out and silicon bring-up experience.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.