Senior Staff Design Verification Engineer — PCIe/CXL Sub-System

Job Title

Senior Staff Design Verification Engineer — PCIe/CXL Sub-System

Role Summary

Lead verification of PCIe and CXL subsystems within a Center of Excellence delivering production-ready IP for Marvell SoCs. Work across architecture, RTL, firmware, and validation teams to define verification strategy, implement scalable test environments, and close coverage to signoff.

Experience Level

Senior; typically 5–10 years of ASIC/SoC verification experience.

Responsibilities

Own end-to-end functional and performance verification for PCIe/CXL subsystems from planning through signoff.

• Define and execute verification plans based on protocol specs and micro-architecture requirements.
• Architect and develop scalable UVM/SystemVerilog testbenches for controllers and fabric-level subsystems.
• Integrate and configure PCIe/CXL VIP for subsystem and system-level verification.
• Validate CXL.io, CXL.cache, and CXL.mem protocols including coherency and memory semantics.
• Develop constrained-random and directed test suites to achieve functional and corner-case coverage.
• Debug protocol violations, ordering issues, and coherency bugs using waveforms, logs, and protocol analyzers.
• Implement SystemVerilog Assertions (SVA) for protocol compliance and early bug detection.
• Drive functional, code, and assertion coverage closure and produce coverage reports.
• Validate performance metrics (latency, throughput, QoS) under stress and high-bandwidth workloads.
• Develop automation (Python/Shell) for regression management, log triage, and coverage reporting.
• Collaborate with design, architecture, firmware, and validation teams; mentor junior engineers.

Requirements

Must-have technical skills and experience for successful performance in the role.

• 5–10 years of ASIC/SoC verification experience focused on high-speed interfaces.
• Strong knowledge of PCIe and CXL protocols and architecture.
• Expertise in SystemVerilog and UVM methodology.
• Proven ability to debug complex verification issues and drive resolution.
• Familiarity with industry-standard simulation, waveform debugging, and coverage tools.
• Solid understanding of digital design fundamentals.

Preferred / nice-to-have:

• Experience with assertion-based verification (SVA).
• Exposure to performance modeling, traffic generation, and emulation platforms (e.g., Palladium, Veloce).
• Scripting skills: Python, Perl, or Shell.
• Experience with low-power verification (UPF) and post-silicon bring-up.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.